| 2019 |
N. Bagga, N. Chauhan, S. Banchhor, D. Gupta and S. Dasgupta |
Demonstration of a novel tunnel FET with channel sandwiched by drain, vol. 35 |
Journal of Iopscience Semicond. Sci. Technol. |
SCI |
Q1 |
2.35 |
| 2019 |
N. Bagga, N. Chauhan, D. Gupta, and S. Dasgupta |
A novel twofold tunnel FET with reduced miller capacitance: proposal and investigation |
IEEE Transactions on Electron Devices |
SCI |
Q1 |
3.23 |
| 2022 |
K. S. Johnson, N. Chauhan, A. Bulusu, S. Dasgupta |
Physical Cause and Impact of Negative Capacitance Effect in Ferroelectric P(VDF-TrFE) Gate Stack and Its Application to Landau Transistor |
Open Journal of Ferroelectric, Frequency Control |
SCI |
Q1 |
3.87 |
| 2022 |
S.Yadav, N. Chauhan, S. Banchhor, A. Sharma, R. Chawla, A. Bulusu |
Through-silicon-via induced stress aware FinFET buffer sizing in 3D ICs |
Semiconductor Science and Technology |
SCI |
Q1 |
2.35 |
| 2020 |
S. Banchhor, N. Chauhan and B. Anand |
A Physical Insight into Zero-Temperature Coefficient with Self-Heating Effect in SOI FinFET. |
Semiconductor Science and Technology |
SCI |
Q1 |
2.35 |
| 2021 |
S. Yadav, N. Chauhan, S. Tyagi, A. Sharma, S. Banchhor, R. Joshi, R. Pratap, and Anand Bulusu |
A physical insight into variation aware minimum V DD for deep subthreshold operation of FinFET, vol 36 |
Semiconductor Science and Technology |
SCI |
Q1 |
2.35 |
| 2021 |
N. Chauhan, Om Prakash, Aniket Gupta, Hussam Amrouch |
Performance Optimization of Analog Circuits in Negative Capacitance Transistor Technology,” Microelectronics Journal, Volume 115, |
Microelectronics Journal |
SCI |
Q2 |
2.23 |
| 2021 |
N. Chauhan, C. Garg, S. Deng, A. I. Khan, S. Dasgupta, Anand Bulusu, and Kai Ni |
Impact of Random Spatial Fluctuation in Non-Uniform Crystalline Phases on the Device Variation of Ferroelectric FET |
IEEE Electron Device Letters |
SCI |
Q1 |
4.816 |
| 2021 |
N. Chauhan, C. Garg, A. Sharma, S. Banchhor, A. Doneria, S. Dasgupta, Anand Bulusu, |
"Investigation of Trap-Induced Performance Degradation and Restriction on Higher Ferroelectric Thickness in Negative Capacitance FDSOI FET, |
IEEE transaction on Electron Devices |
SCI |
Q1 |
3.26 |
| 2021 |
N. Chauhan, N. Bagga, S. Banchhor, A. Datta, S. Dasgupta and B. Anand |
Negative to Positive Differential Resistance Transition in Ferroelectric FET: Physical Insight and Utilization in Analog Circuits |
IEEE Transaction of Ferroelectric, Ultrasonic and Frequency Control |
SCI |
Q1 |
3.69 |
| 2021 |
N. Chauhan, N. Bagga, S. Banchhor, C. Garg, A. Sharma, A. Datta, S. Dasgupta, and Anand Bulusu |
BOX engineering to mitigate negative differential resistance in MFIS negative capacitance FDSOI FET: An Analog perspective." Nanotechnology |
IOP Nanotechnology |
SCI |
Q1 |
3.874 |
