PANKAJ KUMAR PAL - Profile Summary
(Electronics & Communication Engineering)
PANKAJ KUMAR PAL
Assistant Professor

Name PANKAJ KUMAR PAL
Phone +91-9568029300
Email [email protected]
Google Scholar Link View
Designation Assistant Professor
Department Electronics & Communication Engineering
Qualification Ph.D. (IIT Roorkee), M.Tech. (NIT Hamirpur)
Date of Birth 1986-09-06
Date of Joining 2016-05-16
Specialization Microelectronics and VLSI Design
Educational Qualification
Name of the Degree Year Of Passing Institute/University
B.Tech. (Electronics & Communication Engineering) 2008 Faculty of Engineering & Technology, Gurukul Kangri University, Haridwar, India
M.Tech. (VLSI Design Automation & Techniques) 2010 National Institute of Technology Hamirpur, H.P., India
Ph.D. (Microelectronics & VLSI Design) 2016 Indian Institute of Technology Roorkee, Uttarakhand, India
Teaching Experience
Programme Name Name of Institute / Universities From To
Assistant Professor (Grade I) Department of Electronics Engineering 2023-09-15 Till Date
Assistant Professor ECE Department, Phonics School of Engineering Roorkee under UTU Roorkee - 247667, Uttarakhand 2010-07-01 2010-10-31
Assistant Professor Department of Electronics & Communication Engineering, Faculty of Engineering & Technology, Gurukul Kangri University Haridwar - 249404, Uttarakhand 2010-11-01 2011-08-04
Teaching Associate Department of Electronics Engineering, National Institute of Technology (NIT), Uttarakhand Srinagar (Garhwal) - 246174, Uttarakhand 2016-01-11 2016-05-16
Assistant Professor (Grade II) Department of Electronics Engineering, National Institute of Technology (NIT), Uttarakhand Srinagar (Garhwal) - 246174, Uttarakhand 2016-05-16 2023-09-15
Administrative Experience
Position Held Department and Organization From To
Faculty Incharge, Institute's Innovation and Incubation Cell R&C Section, NIT Uttarakhand 2023-11-01 Till Date
Faculty In-charge, IPR Cell NIT Uttarakhand (Institute Level) 2020-06-01 Till Date
Faculty In-charge, Time-Table & Class-room Infrastructure Management Satellite Campus, NIT Uttarakhand (Institute Level) 2019-07-15 2020-11-08
Faculty In-charge, Innovation & Incubation Cell Satellite Campus, NIT Uttarakhand (Institute Level) 2019-06-03 2020-05-31
Faculty In-charge, Foreign and Interstate Students NIT Uttarakhand (Institute Level) 2018-07-12 2019-06-02
Head, Dept. of Electronics Engineering, NIT Uttarakhand NIT Uttarakhand (Institute Level) 2016-07-18 2018-07-11
Research Experiences
Research Interest Breif Research Interest
Research Projects
Role Project Type Title Funding Agency From To Amount Status Co-Investigator
Co-Principal-Investigator Sponsored Project IoT-based Multifunctional Scalable Real-Time Farm Monitoring System for Smart Agriculture Agriculture & Water Technology Development Hub (AWaDH) scheme, TIH, IIT Ropar 2021-08-08 Sponsored Project 16.97 Lakhs Ongoing Dr. Ghanapriya Singh, NIT Kurukshetra
Chief Investigator Sponsored Project Special Manpower Development Programme: Chip to System Design (SMDP-C2SD) Ministry of Electronics and Information Technology, Government of India 2016-08-31 Sponsored Project 124.09 Lakhs Completed Dr. Tushar Goel
Journal Publications
Year Author(s) Title & Vol. No. Journal Name Indexing (SCI)
2024 R. Tanwar, O. C. Phukan, G. Singh, P. K. Pal, S. Tiwari “Attention based hybrid deep learning model for wearable based stress recognition,” vol. 127, Part B, Elsevier’ Engineering Applications of Artificial Intelligence SCI
2023 A. Bisht, Y. P. Pundir, and P. K. Pal “Performance Analysis of Nanosheet Transistor with Drain/ Source Extension and High-k Spacer Optimizations for Analog Circuits,” Springer’s Analog Integrated Circuits and Signal Processing SCI
2023 A. Bisht, Y. P. Pundir, and P. K. Pal “Nanosheet Transistor with Inter-bridge Channels for Superior Delay Performance: A Comparative Study,” vol. 15, pp. 5175–5185, Mar. 2023 Springer’s Silicon SCI
2023 Y. P. Pundir, A. Bisht, R. Saha, and P. K. Pal “Effect of Process-Induced Variations on Analog Performance of Silicon-based Nanosheet Transistor,” Springer’s Silicon, vol. 15, pp. 4449–4455, Feb. 2023 Springer’s Silicon SCI
2022 Y. P. Pundir, A. Bisht, R. Saha, and P. K. Pal “Effect of Temperature on performance of 5-nm node Silicon Nanosheet Transistors for Analog Applications,” March 2022 Springer’s Silicon SCIE
2021 Y. P. Pundir, A. Bisht, R. Saha, and P. K. Pal “Air-spacers as Analog-performance booster for 5 nm-node N-channel nanosheet transistor,” vol. 36, no. 9, pp. 095037, Sept. 2021 IOP Semiconductor Science and Technology SCIE
2022 R. Saha, Y. P. Pundir, and P. K. Pal “Comparative Analysis of STT and SOT based MRAMs for Last Level Caches,” vol. 551, pp. 169161, Feb. 2022, Elsevier’ Journal of Magnetism and Magnetic Materials SCIE
2021 R. Saha, Y. P. Pundir, and P. K. Pal “Design of an area and energy-efficient last-level cache memory using STT-MRAM,” vol. 529, pp. 167882, Feb. 2021 Elsevier’ Journal of Magnetism and Magnetic Materials SCIE
2020 Y. P. Pundir, R. Saha, and P. K. Pal “Effect of gate length on performance of 5nm node N-Channel nano-sheet transistors for analog circuits,” vol. 36, no. 1, pp. 015010, Oct. 2020 IOP Semiconductor Science and Technology SCIE
2016 S. Verma, P. K. Pal, S. Mahavar and B. K. Kaushik “Performance Enhancement of STT MRAM Using Asymmetric-k Sidewall-spacer NMOS,” vol.63, no. 7, pp.2771-2776, July 2016 IEEE Transactions on Electron Devices SCI
2015 P. K. Pal, B. K. Kaushik, and S. Dasgupta “Asymmetric dual-spacer tri-gate FinFET device-circuit codesign and its variability analysis,” vol.62, no.4, pp.1105-1112, Apr. 2015 IEEE Transactions on Electron Devices SCI
2014 P. K. Pal, B. K. Kaushik, and S. Dasgupta “Investigation of symmetric dual-k spacer trigate FinFETs from delay perspective,” vol.61, no.11, pp.3579-3585, Nov. 2014 IEEE Transactions on Electron Devices SCI
2014 P. K. Pal, B. K. Kaushik, and S. Dasgupta “Design metrics improvement for SRAMs using symmetric dual-k spacer (SymD-k) FinFETs,” vol.61, no.4, pp.1123-1130, Apr. 2014 IEEE Transactions on Electron Devices SCI
2013 P. K. Pal, B. K. Kaushik, and S. Dasgupta “High-performance and robust SRAM cell based on asymmetric dual-k spacer FinFETs,” vol.60, no.10, pp.3371-3377, Oct. 2013 IEEE Transactions on Electron Devices SCI
Conference Publications
Year Author(s) Title Conference name with place Indexing (SCI)
2010 R.S. Rathore, P. K. Pal, and A. Sharma National Conference on Emerging Technologies and Applications (ETA-2010), Jaipur, Raj., Feb’2010. National Conference
2011 R.S. Rathore, P. K. Pal, and A. Sharma Nat. Conference on Recent Trends in Electronics, Meerut, UP, April’2011. National Conference
2011 P. K. Pal, R.S. Rathore, and A.K. Rana Nat. Seminar on Inno. And Application in Engg. and Applied Sc., Haridwar, UK, Nov’2011. National Seminar
2012 P. K. Pal, B.K. Kaushik, and S. Dasgupta Nat. Seminar on Progress in Electronics and Applied Sc., Haridwar, Uttarakhand, Oct’2012. National Seminar
2022 A. Bisht, Y. P. Pundir, and P. K. Pal 26th International Symposium on VLSI Design and Test (VDAT) at IIT Jammu, India, 17-19 July 2022, pp. xx-xx. Scopus (Accepted)
2020 Y. P. Pundir, R. Saha and P. K. Pal IEEE Intl. Conf. on Advances in Computing, Communication & Materials (ICACCM), Dehradun, India, Aug. 21-22, 2020, pp. 380-384, doi: 10.1109/ICACCM50413.2020.9212882. Scopus
2020 R. Saha, Y. P. Pundir, S. Yadav and P. K. Pal IEEE Intl. Conf. on Advances in Computing, Communication & Materials (ICACCM), Dehradun, India, Aug. 21-22, 2020, pp. 390-393, doi: 10.1109/ICACCM50413.2020.9213015. Scopus
2020 R. Saha, Y. P. Pundir, and P. K. Pal online Intl. Conf. on Communication, Computing and Signal Processing -2020 (CCSP-2020), Jalandhar, Punjab, India, July 23-24, 2020. Other reputed conference
2019 P. Kumar, S. Yadav, and P. K. Pal IEEE 2nd Intl. Conf. Women Institute of Technology Conference on Electrical and Computer Engineering-2019 (WITCON ECE), Dehradun, India, Nov. 22-23, 2019, pp. 183-186, doi: 10.1109/WITCONECE48374.2019.9092925. Scopus
2019 R. Saha, R. K Singh, R. Kumar, G. Singh, T. Goel, and P. K. Pal IEEE 5th Intl. Conf. on Image Information Processing (ICIIP-2019), Solan, India, Nov. 15-17, 2019, pp. 156-160, doi: 10.1109/ICIIP47207.2019.8985727. Scopus
2019 D. S. Kushwaha, A. K. Rai, S. Agrawal, P. K. Pal, and H. K. Singhal IEEE 2nd Intl. Conf. on Innovations in Electronics, Signal Processing and Communication (IESC), Shillong, India, Mar. 1-2, 2019, pp. 301-304, doi: 10.1109/IESPC.2019.8902452. Scopus
2018 R. K. Singh, R. Saha, P. K. Pal, and G. Singh IEEE 4th Intl. Conf. on Research in Computational Intelligence and Communication Networks (ICRCICN), Kolkata, Nov. 22-23, 2018, pp. 130-134, doi: 10.1109/ICRCICN.2018.8718681. Scopus
2018 Manoj Kumar, P. K. Pal, and S. Yadav IEEE 2nd Intl. Conf. on Trends in Electronics and Informatics (ICOEI-2018), Tirunelveli, Tamilnadu, May 11-12, 2018, pp. 1240-1245, doi: 10.1109/ICOEI.2018.8553700. Scopus
2018 Lokanshu Kumar, P. K. Pal, and H. K. Singhal IEEE 2nd Intl. Conf. on Trends in Electronics and Informatics (ICOEI-2018), Tirunelveli, Tamilnadu, May 11-12, 2018, pp. 1235-1239, doi: 10.1109/ICOEI.2018.8553940. Scopus
2016 P. K. Pal, B. K. Kaushik, and S. Dasgupta IEEE Conf. on Emerging Devices and Smart Systems (ICEDSS-2016), Mallasamudram, Tamilnadu, March 4-5, 2016, pp. 13-18, doi: 10.1109/ICEDSS.2016.7587790. Scopus
2015 P. K. Pal, D. Nehra, B. K. Kaushik, and S. Dasgupta IEEE 12th Intl. Conf. on Electrical Engineering/Electronics, Computer, Telecommunications and Information Technology (ECTI-CON-2015), Hua-hin, Thailand, June 24-27, 2015, pp. 1-5, doi: 10.1109/ECTICon.2015.7206988. Scopus
2015 P. K. Pal, S. Verma, B. K. Kaushik, and S. Dasgupta IEEE 11th Intl. Conf. on Electron Devices and Solid-State Circuits (EDSSC 2015), Singapore, June 1-4, 2015, pp. 190-193, doi: 10.1109/EDSSC.2015.7285082. Scopus
2015 S. Mahawar, S. Verma, P. K. Pal, and B. K. Kaushik IEEE 11th Intl. Conf. on Electron Devices and Solid-State Circuits (EDSSC 2015), Singapore, June 1-4, 2015, pp. 701-704, doi: 10.1109/EDSSC.2015.7285214. Scopus
2015 P. K. Pal, B. K. Kaushik, B. Anand, and S. Dasgupta IEEE 16th Intl. Symp. on Quality Electronic Design (ISQED’15), Santa Clara, CA, USA, March 2-4, 2015, pp. 594-598, doi: 10.1109/ISQED.2015.7085494. Scopus
2014 D. Nehra, P. K. Pal, B. K. Kaushik, and S. Dasgupta IEEE 18th of Int. Symp. on VLSI Design and Test (VDAT-2014), Coimbatore, India, July 15-18, 2014, pp.1-6, doi: 10.1109/ISVDAT.2014.6881054. Scopus
2014 P. K. Pal, B. K. Kaushik, and S. Dasgupta IEEE 29th Int. Conf. on Microelectronics (MIEL-2014), Belgrade, Serbia, May 12-15, 2014, pp. 103-106, doi: 10.1109/MIEL.2014.6842096. Scopus
2012 P. K. Pal, P. Singh, B. K. Kaushik, B. Anand, and S. Dasgupta IEEE Annual India Conf. (INDICON-2012), Trivandrum, Kerala, Dec. 7-9, 2012, pp. 915-919, doi: 10.1109/INDCON.2012.6420747. Scopus
2010 P. K. Pal, R.S. Rathore, A.K. Rana, and G. Saini IEEE Int. Conf. on Computer and Communication Technology (ICCCT-2010), Allahabad, UP, Sept. 17-19, 2010, pp.296-301, doi: 10.1109/ICCCT.2010.5640514. Scopus
2010 G. Saini, A.K. Rana, P. K. Pal, and S. Jadav IEEE Int. Conf. on Computer and Communication Technology (ICCCT-2010), Allahabad, UP, Sept. 17-19, 2010, pp.302-305, doi: 10.1109/ICCCT.2010.5640528. Scopus
2011 R.S. Rathore, P. K. Pal, and A. Sharma 1st Int. Conf. on Adaptive Computing in Various Engineering Applications (ICACTEA-2011), Jaipur, Rajasthan, Feb. 24-26, 2011, pp. 1-4. Other reputed conference
Book/Chapters Written
Type Title Publisher Authors ISBN/ISSN No. Year
Book Spacer Engineered FinFET Architectures: High-Performance Digital Circuit Applications CRC Press,Taylor & Francis Brajesh Kumar Kaushik, Sudeb Dasgupta, Pankaj Kumar Pal 9781315191089 2017
Chapters Optimization of underlap FinFETs and its SRAM performance projections using high-k spacers Springer LNCS P. K. Pal, B. K. Kaushik, and S. Dasgupta 978-3-642-42024-5 2013
Chapters Electro-Thermal Analysis of Vertically Stacked Gate All Around Nano-sheet Transistor Communications in Computer and Information Science, vol 1687. Springer Bisht, A., Pundir, Y.P., Pal, P.K. 978-3-031-21514-8 2022
Research Supervision
Programme Name Scholar Name Research Topic Status Year Co-Superivisor
Ph.D Ritu Tanwar A Probabilistic framework of affect recognition using physiological signals Ongoing Dr. Ghanaprya Singh, NIT Kurukshetra
B.Tech Mr. Abhinav Kumar (BT15ECE046) Post Silicon validation and bench automation for Pressure Sensors Completed Internship at NXP Semiconductor Pvt. Ltd.
B.Tech Mr. Tarun Kumar (BT17ECE051) Detection of Diabetic Retinopathy and Integrating with Cloud Completed NA
M.Tech Mr. Abhishek Goel (MT20ECE004) Study of Impact of Radiation hardened dual-port SRAM Completed Dr. Hemant Kumar Singhal
M.Tech Ms. Pranoti Gogulwar (MT18ECE004) Post-Silicon Functional Validation of Gateway Completed at NXP Semiconductors (Internship)
M.Tech Mr. Diwakar Mishra (MT17ECE004) Automated Workload Analysis and Characterization Completed Dr. T. S. Arora, (Internship at Intel)
M.Tech Mr. Priyesh Kumar (MT17ECE002) Analysis of Nano-sheet FETs from device and circuit perspectives Completed NA
M.Tech Mr. Lokanshu Kumar (MT16ECE013) Shared Bit-line Architecture of Magnetic Random Access Memory Completed Dr. Hemant Kumar Singhal
M.Tech Mr. Davuluri Srikanth (MT16ECE010) Parasitic Extraction in Novel MOS Based Devices Completed NA
M.Tech Mr. Manoj Sharma (MT16ECE008) Radiation Hardened Pipelined ADC Completed Dr. Sarita Yadav
M.Tech Mr. Abhishek Kumar (MT16ECE007) Tunnel Field Effect Transistor Based SRAM Design Completed NA
M.Tech Mr. Sudhir Singh (MT16ECE005) Negative Capacitance Field Effect Transistor Completed Dr. Tushar Goel
M.Tech Mr. Deependra Singh Kushwaha (MT16ECE002) A Cascode Inductive Source Degeneration Low Noise Amplifier Design Completed Dr. Hemant Kumar Singhal
Ph.D Mr. Arvind Bisht (DT19ECJ010) Study of Electrothermal characteristics and dielectric effects in novel MOS based devices Ongoing NA
Ph.D Mr. Varun Kumar Kakar (DT19ECJ001) Design and Analysis of Nanoscale devices under Thermal Effects Ongoing NA
Ph.D Mr. Rajesh Saha (DT17ECJ002) Design of Energy-efficient SPIN-based Memories for Cache Applications Submitted NA
Ph.D Mr. Yogendra Pratap Pundir (DT17ECJ001) Performance Analysis of Nano-sheet transistors for Analog Applications Completed NA
Patents
Name Reg./Ref.No. Date Of Award/Filling Organization Status
Expert Talks
Year Title Place Description
Jan. 22, 2022 Online Expert Talk on INNOVATIONS IN VLSI TESTING Siddharth Institute of Science and Technology, Puttur Online Expert Talk organized by IIC Council
March 28- April 1, 2022 Invited Talk Dr. B. R. Ambedkar NIT Jalandhar (Punjab) India STC (online) on “Emerging Trends and Modeling in Advanced Functional Materials & Devices”
22-26 Aug 2022 Invited Talk National Institute of Technical Teachers Training and Research (NITTTR) Chandigarh Online One week Short Term Course on “Nanoelectronics Devices and Circuits Design” for faculty members from engineering colleges and polytechnics at remote locations
03rd – 14th October, 2022 Invited Talks Department of Electrical and Electronics Engineering and the Department of Applied Science, ABV-IIITM Gwalior, M.P. Two-week (First week online + second week offline) AICTE Training and Learning (ATAL) Academy-sponsored FDP on "Advancement in VLSI Interconnects and Nanoscale Devices"
2017 Semiconductor Device Physics & Circuits Government Mahila Engineering College, Ajmer Expert Talk
Consultancy
Title of Consultancy Client Organization Faculty Involved Amount(INR) Status
International & National Exposure
Sr.No. Title Description
Honors & Recognitions Achieved
Sr.No. Title Activity Given By Year
Young Professional Star of the Month (Oct’22) Academic & Research IEEE UP Section 2022
Elevated to IEEE Senior Member Membership Institute of Electrical and Electronics Engineers (IEEE) 2021
Awarded by Director's Medal for obtaining highest CGPA (branch topper) in the year 2010 during M.Tech., E&CE Department National Institute of Technology, Hamirpur 2012