| 2023 |
A. Bisht, Y. P. Pundir, and P. K. Pal |
“Performance Analysis of Nanosheet Transistor with Drain/ Source Extension and High-k Spacer Optimizations for Analog Circuits,” |
Springer’s Analog Integrated Circuits and Signal Processing |
SCI |
Q3 |
1.4 |
| 2023 |
A. Bisht, Y. P. Pundir, and P. K. Pal |
“Nanosheet Transistor with Inter-bridge Channels for Superior Delay Performance: A Comparative Study,” vol. 15, pp. 5175–5185, Mar. 2023 |
Springer’s Silicon |
SCI |
Q2 |
2.94 |
| 2023 |
Y. P. Pundir, A. Bisht, R. Saha, and P. K. Pal |
“Effect of Process-Induced Variations on Analog Performance of Silicon-based Nanosheet Transistor,” Springer’s Silicon, vol. 15, pp. 4449–4455, Feb. 2023 |
Springer’s Silicon |
SCI |
Q2 |
2.94 |
| 2022 |
Y. P. Pundir, A. Bisht, R. Saha, and P. K. Pal |
“Effect of Temperature on performance of 5-nm node Silicon Nanosheet Transistors for Analog Applications,” March 2022 |
Springer’s Silicon |
SCIE |
Q2 |
2.474 |
| 2021 |
Y. P. Pundir, A. Bisht, R. Saha, and P. K. Pal |
“Air-spacers as Analog-performance booster for 5 nm-node N-channel nanosheet transistor,” vol. 36, no. 9, pp. 095037, Sept. 2021 |
IOP Semiconductor Science and Technology |
SCIE |
Q1 |
2.361 |
| 2022 |
R. Saha, Y. P. Pundir, and P. K. Pal |
“Comparative Analysis of STT and SOT based MRAMs for Last Level Caches,” vol. 551, pp. 169161, Feb. 2022, |
Elsevier’ Journal of Magnetism and Magnetic Materials |
SCIE |
Q2 |
3.097 |
| 2021 |
R. Saha, Y. P. Pundir, and P. K. Pal |
“Design of an area and energy-efficient last-level cache memory using STT-MRAM,” vol. 529, pp. 167882, Feb. 2021 |
Elsevier’ Journal of Magnetism and Magnetic Materials |
SCIE |
Q2 |
3.097 |
| 2020 |
Y. P. Pundir, R. Saha, and P. K. Pal |
“Effect of gate length on performance of 5nm node N-Channel nano-sheet transistors for analog circuits,” vol. 36, no. 1, pp. 015010, Oct. 2020 |
IOP Semiconductor Science and Technology |
SCIE |
Q1 |
2.361 |
| 2016 |
S. Verma, P. K. Pal, S. Mahavar and B. K. Kaushik |
“Performance Enhancement of STT MRAM Using Asymmetric-k Sidewall-spacer NMOS,” vol.63, no. 7, pp.2771-2776, July 2016 |
IEEE Transactions on Electron Devices |
SCI |
Q1 |
2.913 |
| 2015 |
P. K. Pal, B. K. Kaushik, and S. Dasgupta |
“Asymmetric dual-spacer tri-gate FinFET device-circuit codesign and its variability analysis,” vol.62, no.4, pp.1105-1112, Apr. 2015 |
IEEE Transactions on Electron Devices |
SCI |
Q1 |
2.913 |
| 2014 |
P. K. Pal, B. K. Kaushik, and S. Dasgupta |
“Investigation of symmetric dual-k spacer trigate FinFETs from delay perspective,” vol.61, no.11, pp.3579-3585, Nov. 2014 |
IEEE Transactions on Electron Devices |
SCI |
Q1 |
2.913 |
| 2014 |
P. K. Pal, B. K. Kaushik, and S. Dasgupta |
“Design metrics improvement for SRAMs using symmetric dual-k spacer (SymD-k) FinFETs,” vol.61, no.4, pp.1123-1130, Apr. 2014 |
IEEE Transactions on Electron Devices |
SCI |
Q1 |
2.913 |
| 2013 |
P. K. Pal, B. K. Kaushik, and S. Dasgupta |
“High-performance and robust SRAM cell based on asymmetric dual-k spacer FinFETs,” vol.60, no.10, pp.3371-3377, Oct. 2013 |
IEEE Transactions on Electron Devices |
SCI |
Q1 |
2.913 |
